In current processes, an eNVM utilizes a floating-gate (FG) memory as depicted in FIGS. 1A and 1B (side view) for a 2T memory cell, which includes a select transistor 100 (logic cell) and a memory cell 101. The logic cell 100 employs a dual polysilicon (poly) stack with an access gate (AG) 103, and the memory cell 101 includes a floating poly gate (FG) 105, and a control gate (CG) 107. Each stack includes an insulating layer on upper side of a substrate 111, for example a tunnel oxide (TunOx) layer 109a under FG 105 and a dielectric layer 109b (different from TunOx 109a) under AG 103, and a blocking oxide (BlockOx) layer 113 on top of the AG 103 and FG 105 layers. However, this approach increases process complexity such as step height differences between the logic 100 and memory 101 cells causing contact (CA) landing issues. Additionally, both AG/FG and CG need to be doped and a special process is required for landing a contact on the AG. Moreover, like most n+ poly CG/FG memory devices, erase saturation level could be an issue that requires consideration. Overall, the current integration scheme requires additional process steps (e.g., 7 to 9 additional masks), which increase cost and decrease efficiency of the integration process.
A need therefore exists for simpler and more efficient eNVM and RMG compatible integration schemes and enabling methodology.